C HAPTER 1: D ESIGN F LOW
D ESIGN M ETHODOLOGIES AND P LANNING
Design Methodologies and Planning
When you are creating a new design, it is important to consider the design
methodologies the Quartus II software offers, including incremental
compilation design flows and block-based design flows. You can use these
design flows with or without EDA design entry and synthesis tools.
Incremental Design Flows
Your design flow affects how much impact design partitions have on design
optimization, and how much design planning may be required to obtain
optimal results. In the standard incremental compilation flow, the design is
divided into partitions, which can be compiled and optimized together as
parts of one Quartus II project. If another team member or IP provider is
developing source code for the design, they can functionally verify their
partition independently, and then simply provide source code for the
partition to the project lead for integration into the larger design. If the
project lead wants to compile the larger design when source code is not yet
complete for a partition, they can create an empty placeholder for the
partition to facilitate compilation until the actual partition code is ready.
Compiling all design partitions in a single Quartus II project ensures that all
design logic is compiled with a consistent set of assignments and allows the
software to perform global placement and routing optimizations. Compiling
all design logic together is beneficial for FPGA design flows because in the
end all parts of the design must use the same shared set of device resources.
If required for third-party IP delivery, or in cases where designers can not
access a shared or copied top-level project framework, you can create and
compile a design partition logic in isolation and export a partition that is
included in the top-level project. If this type of design flow is necessary,
planning and rigorous design guidelines may be required to ensure that
designers have a consistent view of project assignments and resource
allocations. Therefore developing partitions in completely separate
Quartus II projects can be more challenging than having all source code
within one project or developing design partitions within the same top-level
project framework.
14
I NTRODUCTION TO THE Q UARTUS II S OFTWARE
A LTERA C ORPORATION
相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
SW006015 C COMPILER MPLAB C32
SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
SW300010-EVAL SPEECH RECOG LIBRARY-EVAL ONLY
SW300040-EVAL LIBRARY NOISE SUPPR-EVAL ONLY
SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
相关代理商/技术参数
SW-QUARTUS-SE-FLT 功能描述:开发软件 FLOATING LICENSE FOR QUARTUS II RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
SWR 制造商:RUBYCON 制造商全称:RUBYCON CORPORATION 功能描述:METALLIZED POLYESTER FILM CAPACITORS
SWR-1 制造商:Sunhayato 功能描述:
SWR100MD 功能描述:基准电压& 基准电流 Sine Wave Ref. Custom RoHS:否 制造商:STMicroelectronics 产品:Voltage References 拓扑结构:Shunt References 参考类型:Programmable 输出电压:1.24 V to 18 V 初始准确度:0.25 % 平均温度系数(典型值):100 PPM / C 串联 VREF - 输入电压(最大值): 串联 VREF - 输入电压(最小值): 分流电流(最大值):60 mA 最大工作温度:+ 125 C 封装 / 箱体:SOT-23-3L 封装:Reel
SWR-10-12 制造商:Raxxess 功能描述:Wall Mount 10RU Hinged Rack with 12" Usable Depth
SWR1062/C 制造商:BRITOOL 功能描述:RING SPANNER CRANK SLOG 1 1/16AF
SWR1125 制造商:BRITOOL 功能描述:RING SPANNER FLAT SLOG 1 1/8AF
SWR1187 制造商:BRITOOL 功能描述:RING SPANNER FLAT SLOG 1 3/16AF